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CS51220 Feed Forward Voltage Mode PWM Controller with Programmable Synchronization
CS51220 is a single output PWM Controller with switching frequency up to 500 kHz. The feed forward voltage mode control provides excellent line regulation for wide input range. This PWM controller has a synchronization output allowing programmable phase delay. For overcurrent protection, the "soft hiccup" technique effectively limits the output current with maximum flexibility. In addition, this device includes such features as: soft start, pulse-by-pulse current limit, programmable foldback current limit, volt-second clamping, maximum duty cycle, overvoltage and undervoltage protection, and synchronization input. The CS51220 is available in 16 SO narrow surface mount package.
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1
SO-16 D SUFFIX CASE 751B
* * * * * * * * * * * * *
Features Constant Frequency Feed Forward Voltage Mode Control Programmable Pulse by Pulse Overcurrent Limit Programmable Foldback Overcurrent Limit with Delay Soft Hiccup Overcurrent Protection with Programmable Foldback Frequency Synchronization Output with Programmable Phase Delay Synchronization Input to Higher or Lower Frequency Direct Connection to External Opto Isolators Logic Gate Output Signal Accurate Volt-Second Clamping Programmable Soft Start Logic Input to Disable IC Line Overvoltage and Undervoltage Monitoring 3.3 V 3% Reference Voltage Output
PIN CONNECTIONS AND MARKING DIAGRAM
VO GND VCC VREF ISET 1 CS51220 AWLYWW 16 SYNCO VSD SS COMP FF DISABLE SYNCI CT
ISENSE OV UV
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS51220ED16 CS51220EDR16 Package SO-16 SO-16 Shipping 48 Units/Rail 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2006
July, 2006- Rev. 7
1
Publication Order Number: CS51220/D
D3
R4 10
L2
36-72 V C3 1.5 F 100 V MMSD4148T1 C5 0.1 F C12 100 pF D5B MBRB2535CTL R13 100 D4 R14 R15 36 10 k R2 174 k R1 100 k
R3 10
MMSD4148T1
VIN
1.0 H
C1 0.2 F 100 V
GND T1 L1
Q2 MMFT1N10E C4 470 pF D1 9.1 V MMSZ5239B D2 15 V MMSZ5245B
C2 0.1 F 500 V
70:1 T2
R23 10
6.8 H
C17 330 F D5A MBRB2535CTL
U1 VCC ISENSE VO GND SS SYNCI SYNCO
C10 0.1 F
VOUT 3.3 V @ 5.0 A
FF
R7 150 k
R5 10 k
VREF CT VSD ISET UV
C8 390 pF
20:5
C12 680 pF
C18 330 F
VORTN
CS51220
CS51220
ENABLE SYNC OUT SYNC IN
NC GND
NCP4414
Figure 1. Application Diagram, 48 V to 3.3 V Converter
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OV COMP DISABLE VDD INA U4 VDD OUT OUT GND
C7 1000 pF R12 11.8 k C11 1.0 F R17 182 U2 MOC213 R24 3.3 k R23 220
2 R14 2.0 k
C6 0.1 F
R6 7.5 k
R16 10 Q1 MTB20N20E C13 100 pF 200 V R21 40.2 k
R8 64.9 k
R9 R11 510 k 510 k
R20 2.21 k
R19 3.92 k R18 1.0 K
C15 0.022 F C14 100 pF
U3 TLV431ASNT1 R22 24.3 k
C9 1000 pF
R10 15 k
CS51220
MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Storage Temperature Range, TS ESD Susceptibility (Human Body Model) Thermal Resistance, Junction-to-Case, RJC Thermal Resistance, Junction-to-Ambient, RJA Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 -65 to +150 2.0 28 115 230 peak Unit C C kV C/W C/W C
MAXIMUM RATINGS
Pin Name Gate Logic Output Current Sense Input Timing Capacitor Feed Forward Error Amp Output Feedback Voltage Sync Input Power Down Input Undervoltage Overvoltage Current Set Soft Start Power Supply Sync Output Reference Voltage Sync Delay Ground Pin Symbol VO ISENSE CT FF COMP VFB SYNCI DISABLE UV OV ISET SS VCC SYNCO VREF VSD GND VMAX 20 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 20 V 20 V 6.0 V 6.0 V 6.0 V 6.0 V 20 V 20 V 6.0 V 6.0 V N/A VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V N/A ISOURCE 100 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 100 mA Internally Limited 1.0 mA 50 mA ISINK 100 mA 10 mA 10 mA 100 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 10 mA 50 mA 100 mA 10 mA 1.0 mA N/A
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otherwise specified.)
ELECTRICAL CHARACTERISTICS (-40C < TA < 85C; -40C < TJ < 125C; 4.7 V < VCC < 16 V; CT = 390 pF; unless
Characteristic Supply Voltage/Current Start Threshold Stop Threshold Hysteresis ICC @ Startup ICC Operating, Low VCC ICC Operating, High VCC Reference Voltage Total Accuracy Line Regulation Load Regulation Operating Life Shift Fault Voltage VREF OK Voltage VREF OK Hysteresis Current Limit Oscillator Frequency Accuracy Temperature Stability Max Frequency Duty Cycle Peak Voltage Valley Voltage Discharge Current Charge Current Synchronization SYNCI Input Threshold SYNCI Input Resistance Minimum Sync Frequency Minimum Input Sync Pulse Width SYNCO Output High SYNCO Output Low SYNCO Delay Time fSYNC = 500 kHz VSYNC = 0.5 Reduction of nominal frequency. - RSYNCO = 5.0 k, VCC = 8.0 V Sink 1.0 mA, VSD = 2.5 V VCT = 1.5 V, Toggle VSD 1.0 50 25 - 5.0 - 100 2.0 150 - - 6.5 0.2 200 3.0 250 - 200 7.5 0.4 300 V k % ns V V ns Note 2 Note 2 VCT = 1.5 V VCT = 1.5 V Note 2 Note 2 - - 223 - 500 80 1.9 0.85 0.70 127 266 8.0 - 85 2.0 0.90 0.85 150 309 - - 90 2.1 0.98 1.05 183 kHz % kHz % V V mA A VREF = 2.5 V 0 mA < IREF < 2.0 mA IREF = 2.0 mA 0 mA < IREF < 2.0 mA, VCC = 8.0 V T = 1000 Hrs., Note 2 - - - 3.2 - - - 2.8 2.9 50 2.0 3.3 6.0 6.0 4.0 2.95 3.05 100 25 3.4 20 15 20 3.1 3.2 150 65 V mV mV mV V V mV mA Start - Stop VCC < UVL Start Threshold 4.7 V < VCC < 10 V 10 V < VCC < 16 V - - 4.0 3.3 400 - - - 4.4 3.8 600 - - - 4.7 4.1 1000 500 7.5 9.0 V V mV A mA mA Test Conditions Min Typ Max Unit
2. Guaranteed by design. Not tested in production.
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CS51220
otherwise specified.)
ELECTRICAL CHARACTERISTICS (continued) (-40C < TA < 85C; -40C < TJ < 125C; 4.7 V < VCC < 16 V; CT = 390 pF; unless
Characteristic Output (continued) High Saturation Voltage Low Saturation Voltage Pull Down Resistance Rise Time Fall Time Feed Forward Discharge Voltage Discharge Current FF to VO Delay FF Clamp Voltage COMP Switch Off Voltage Overcurrent Protection Overcurrent Comparator DC Offset ISENSE Attenuation ISENSE Input Resistance ISENSE to GATE Delay ISET Foldback Sink Current External Voltage Monitors Overvoltage Threshold OV Hysteresis Current Undervoltage Threshold UV Hysteresis Soft Start Charge Current Discharge Current OC Delay Discharge Current SS Clamp Voltage Discharge Voltage Soft Start Fault Voltage Hiccup Delay Discharge Voltage Disable DISABLE Input Threshold DISABLE Input Resistance DISABLE Operation Current, Low VCC DISABLE Operation Current, High VCC VDISABLE = 0.5 V 4.7 V < VCC < 10 V 10 V < VCC < 16 V - 1.0 50 - - 2.0 150 - - 3.0 250 800 1600 V k A A SS = 1.5 V SS = 1.5 V, UV = 1.5 V SS = 2.85 V, ISET = 0.5, ISENSE = 0.5 V - - OV = 2.5 V or UV = 0.85 V - 35 4.0 35 2.7 0.25 - 0.08 50 5.0 50 2.9 0.3 0.1 0.1 65 7.0 65 3.1 0.35 0.2 0.12 A A A V V V V OV pin increasing OV = 2.15 V UV pin decreasing - 1.9 10 0.95 25 2.0 12.5 1.00 75 2.1 15 1.05 125 V A V mV VISET/VISENSE VISENSE = 0 V VISET = 0.5 V ISET = 0.5 V, SS = 1.5 V and ISENSE = 0.5 V - 180 0.9 40 50 12 200 0.94 82 100 15 215 0.98 150 175 18 mV V/V k ns A IFF = 2.0 mA FF = 1.0 V Connect VO to FF, Measure min. pulse width. - VFF = 0.2 V, Ramp down VCOMP VFF = 0.2 V, Ramp down VCOMP -40C 0.25 2.0 50 1.15 0.8 1.4 0.35 10 75 1.3 1.4 1.6 0.45 30 150 1.45 1.7 1.7 V mA ns V V V VCC - VO, VCC = 10 V, ISOURCE = 100 A VO - GND, ISINK = 100 A ISINK = 100 A VCC = 10 V, 1.0 V < VO < 6.0 V; 50 pF load VCC = 10 V, 1.0 V < VO < 6.0 V; 50 pF load - - 25 - - 1.4 0.7 50 35 25 2.0 1.0 75 80 50 V V k ns ns Test Conditions Min Typ Max Unit
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PACKAGE PIN DESCRIPTION
PACKAGE PIN # 16 Lead SO Narrow 1 2 3 4 5 PIN SYMBOL VO GND VCC VREF ISET FUNCTION Logic output connecting to external gate driver. Ground. Supply Voltage. 3.3 V reference voltage output. Voltage at this pin sets pulse-by-pulse overcurrent threshold. When the ISENSE exceeds ISET for a sustained period of time, a sink current is generated at this pin. Along with external resistors, this current provides a foldback overcurrent threshold. The sink current is disabled periodically for restart. Current sense input for overcurrent protection. Overvoltage protection monitor. Undervoltage protection monitor. Timing capacitor CT determines oscillator frequency. By applying sync pulses to this pin, the IC can be synchronized to frequencies ranging from 25% slower to several times faster than the internal oscillator frequency. Disable mode input pin. A voltage greater than 3.0 V turns off the whole IC. Feed forward input for PWM ramp. This pin allows external connection to make the ramp adjustable to the input line. This pin carries feedback error signal from an external amplifier. Internally, it connects to the PWM controller. A capacitor is connected to this pin for Soft Start and soft hiccup timing. The voltage at this pin programs the delay of the SYNCO output in reference to the internal oscillator. Sync output.
6 7 8 9 10
ISENSE OV UV CT SYNCI
11 12 13 14 15 16
DISABLE FF COMP SS VSD SYNCO
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CS51220
VCC
+ -
+ -
UVL Comparator VREF = 3.3 V Charge 3.1 V Off SS SS SS Clamp
Discharge
VREF - + VREF COMP
DISABLE X0.94 ISENSE ISET
-+
200 mV
+ ILIM - Ifoldback
OC
SS Discharge
COMP
Soft Hiccup
SS low SS
SS low SS COMP
1.3 V SS CLK MIN - + PWM COMP
- +
0.3 V
GND
FF
RQ Fault Latch Q S SET DOMINANT - +
2.0 V OV
OV COMP - + UV COMP S Q OSC R RESET DOMINANT VO UV 1.0 V
SYNCO VSD SYNCI CT
Figure 2. Block Diagram
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CS51220
APPLICATIONS INFORMATION THEORY OF OPERATION
Feed Forward Voltage Mode Control
VOUT COMP
Conventional voltage mode control uses a fixed ramp signal for pulse width modulation, typically utilizing the oscillator output as the ramp signal. Since the only feedback signal comes from the output, this results in inferior line regulation and audio susceptibility. A significant improvement in line regulation and line transient response can be achieved using Feed Forward Voltage Mode Control, implemented using the CS51220 controller. The enhancement comes from generating the ramp signal using a pull-up resistor from the FF pin to the line voltage and a capacitor to ground. The slope of the ramp then depends on the line voltage. At the start of each switch cycle, the capacitor connected to the FF pin is charged through the resistor connected to the input voltage. Meanwhile, the VO pin goes high to turn on a power mosfet through an external gate driver. When the rising FF pin exceeds the COMP input pin, as driven through the regulation feedback loop, VO goes low and turns off the external switch. Simultaneously, the FF capacitor is quickly discharged and set for the next switching cycle. Overall, both input and output voltages control the dynamics of the duty cycle. As illustrated in Figure 3, with a fixed input voltage the output voltage is regulated solely by the error amplifier. For example, an elevated output voltage pulls down the COMP pin through an external error amplifier. This in turn causes duty cycle to decrease. On the another hand, if the input voltage varies, the slope of the FF pin ramp reacts correspondingly and immediately. As an example shown in Figure 4, when the input voltage goes up, the slope of the ramp signal increases, which reduces duty cycle and counteracts the change. For line variations, feed forward control requires less response from the error amplifier, which improves the transient speed and DC regulation.
FF VIN CT VO
Figure 3. Pulse Width Modulated by the Output Voltage with a Constant Input Voltage
VIN COMP
FF VOUT CT VO
Figure 4. Pulse Width Modulated by the Input Voltage with a Constant Output Voltage
The feed forward feature can also be employed for volt-second clamp, which limits the maximum product of input voltage and switch on time. This clamp is used in circuits, such as forward and flyback converters, to prevent the transformer from saturating. Calculations used in the design of the volt-second clamp are presented in the Design Guidelines section on page 12.
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CS51220
VCC Power Up and Fault Conditions
During power up, an undervoltage lockout comparator monitors VCC and disables VREF, (which in turn disables the entire IC), until the VCC voltage reaches its start threshold. Hysteresis prevents "chattering" caused by the source impedance of the VCC supply. VREF can also be disabled using the Disable input pin, which is active high. An internal pull-down resistor ensures the IC will start up if the Disable pin is allowed to float. In VCC or Disable lockout mode, the output stage is held low by the output pull-down resistance. After VREF turns on, there are three conditions that can cause fault mode: 1. The 3.3 V VREF is below regulation, 2. The OV pin rises above overvoltage threshold, or 3. The UV pin falls below undervoltage threshold. Fault detection will cause the VO output to go low and the SS pin to discharge. The UV and OV inputs are typically used to monitor the input line voltage. The undervoltage comparator has a built-in hysteresis voltage, while the hysteresis for the OV comparator is programmable through a current sourced from the pin when above the threshold, and the equivalent external resistance. The fault condition can only be reset after the SS pin has been completely discharged and all faults have been removed. After a fault is removed or upon initial startup, the SS pin charges at a rate determined by an internal charge current and an external capacitor. The rising voltage on the SS pin will override the regulation feedback voltage on the COMP pin and clamp the duty cycle, helping to reduce any in-rush current during startup. The duration of the Soft Start is typically set with a capacitor from 0.01 F to 0.1 F.
Overcurrent Protection
The CS51220 uses the "soft hiccup" technique to provide an adjustable and predictable overcurrent limit. By choosing external component values the designer can select pulse-by-pulse current limit, soft hiccup current limit or hard hiccup limit. Normal pulse-by-pulse current limit can be obtained by selecting the ISET resistor values for a low Thevenin
resistance to the ISET pin. However with normal pulse-by-pulse current limit, the secondary currents during short circuits may be several times the maximum output current. Soft hiccup limit can be obtained by setting the ISET resistor values for a higher thevenin resistance. During overcurrent conditions, the ISET level will fold back, after a short delay, to reduce the pulse by pulse threshold. If desired, the short circuit current can be chosen to be equal to or even less than the maximum output current. During soft hiccup the circuit will periodically disable the foldback and attempt to restart. Hard hiccup limit can be obtained by setting the ISET resistor values so that the ISET pin is held below 200 mV during foldback. During overcurrent conditions, the ISET level will fold back, after a short delay, preventing any gate pulses. When the SS capacitor is completely discharged, the circuit will attempt restart. This configuration provides the lowest power dissipation during short outputs. The circuit functions can be best described by discussing the block diagram and illustrations of expected waveforms. Actual waveforms, values and circuit configurations from a design will be used. The design is from the 5.0 V supply of a dual synchronized converter. The current is monitored with a voltage at the ISENSE pin. The ISENSE signal is slightly attenuated DC shifted by 200 mV, and is compared with the threshold voltage programmed by the voltage at the ISET pin. If the current signal reaches the threshold voltage, the overcurrent comparator resets the VO latch and terminates the VO pulse. The overcurrent comparator has a maximum common mode input voltage of 1.8 V. However, an ISET voltage below 1.0 V is desirable for reducing the comparator's propagation delay. During initial turnon of the power supply, normal pulse-by-pulse overcurrent control is used to protect the power supply switches. This is accomplished by comparing the voltage at the ISENSE input to the voltage at the ISET pin and using this to limit the duty factor of VO, the gate drive signal. This current limit control is maintained until the SS voltage reaches 2.9 V.
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The block diagram of the soft hiccup circuit is shown in Figure 5. When overcurrent occurs and the SS is above 2.9 V, the OC pulses set the OC latch. The output of the OC latch turns on the OC delay discharge current to ramp down the SS voltage. This SS discharge ramp down is at a rate of 50 A while the SS voltage is above 2.8 V. The level between 2.9 V and 2.8 V is called the hiccup delay discharge voltage. The time to cross this voltage creates a short delay. This delay is useful so that a quick transient overcurrent condition can be controlled and still allow the supply to return immediately to normal operation. After reaching the hiccup delay discharge voltage, the SS current is reduced to 5.0 A and the ISET foldback current is turned on at 15 A. It is the ISET foldback current that adjusts the ISET level to establish a new lower ISENSE current limit level. See Figure 6 for details.
SS + 2.9 V OC CLK SS low - Peak COMP S Reset Trig One Shot - 2.8 V + Delay COMP N00C Q SS Discharge
The NOOC or SS low (VSS < 0.3 V) signal can reset OC latch at any time. This event turns off ISET foldback and allows the recharging of the SS capacitor. Therefore, the IC allows the power supply to restart periodically or after the overcurrent condition is cleared. The OC latch can not be set until the SS capacitor is fully charged. To implement "hard hiccup" which disables the VO completely when the SS voltage is ramping down, select a resistor value greater than 3.3 V/ISET for R1 in Figure 6, and saturate the internal ISET current source. Since the saturation voltage is less than the DC shift applied to the ISENSE signal, the OC comparator output is always high and in turn keeps the VO low. Figure 7 demonstrates the interactions among the voltage of SS, ISET and internal signal OC. Figure 8 further describes the specifications associated with the soft hiccup. The ratio among the charge time, delay time and discharge time is given at the bottom of Figure 8.
SS 2.9 V 2.8 V 0.3 V
R OC Latch Foldback ON
ISET
Figure 5. The Block Diagram of the Soft Hiccup Operation
A circuit monitors the OC pulses. If the OC pulses cease for 50 s, the NOt-OverCurrent (NOOC) signal is generated. This NOOC signal resets the OC Latch and allows the SS capacitor to charge back up allowing the output to reestablish regulation. For an equivalent circuit shown in Figure 6, the ISET current reduces the overcurrent threshold and sets the new threshold at
VI(SET) + (3.3 * ISET
VREF R1 ISET Pin
OC 50s
Figure 7. Illustrative Waveforms of the Soft Hiccup Operation
Charge Voltage Charge Current OC Delay Dischage Current
Hiccup Delay Discharge Voltage
R1)
R2 (R1 ) R2)
Discharge Voltage 26 1
Dischage Current 250
R2 ISET
Figure 8. The SS Pin Voltage Under Ramp Up and Overcurrent Condition and Associated Specifications.
Figure 6. The Voltage Divider Used at the ISET Pin Allows the ISET Foldback Current to Reduce the Overcurrent Threshold
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The effect of the soft hiccup can be observed in Figure 9, which shows the output voltage as load increases. The output is maintained at the regulation value of 5.0 V until it goes into current limit. At the point of overcurrent inception (A), the current limit level changes to a lower level (B). The switchback to a lower current limit level can be seen as the bottom curve in Figure 9.
6 5 Output Voltage (V) 4 3 2 1 0
A
The middle trace is a digitizing `scope trace of the current sense line. The scope interprets the voltages as an average voltage. This voltage is actually a narrow duty cycle peak voltage representing the peak current level in the switching transistor. The actual peak voltages can be seen in the Figure 11. The peaks are 0.85 V at full load, reducing to 0.6 V peak at the reduced short circuit level. The 1.1 V peak is the full short circuit current while SS ramps back up. The 0.32 V level is the normal load resistance, while ISET is still on. The 1.0 V surge is created by ramp up into a normal 5.0 A load and followed by the 0.85 V at normal load.
Peak Detect Setting
B 0 2 4 6
Load Current (A)
Figure 9. Overcurrent In a 5.0 V Output Converter Using Soft Hiccup
A typical overload scenario is shown in Figure 10. The top trace is the voltage on the Soft Start (SS) pin. The initial high discharge rate can be seen transitioning to a 40 ms discharge period. During this period the ISET establishes a lower current limit level. The bottom trace shows the output current. The initial current spike is the output capacitors discharging. The next level around 4.0 A is the short circuit current level set by the ISET current. The output then turns off allowing the current to reduce to a level that does not cause overcurrent pulses. This releases the SS pin to ramp back up. During ramp up, the output is still shorted as noted by the 8.0 A current level. When SS reaches the 2.9 V level, the short is again recognized and ISET is turned back on shifting the short circuit current level.
Figure 11. Over-Load Current and ISENSE Voltage Oscillator and Synchronization
Figure 10. Over-Load Current and Soft Start Waveforms
The switching frequency is programmable through a capacitor connected to the CT pin. When the CT pin voltage reaches peak voltage (2.0 V), the internal discharge current discharges the CT capacitor and VO stays low. When the CT voltage declines to valley voltage (0.9 V), the current source toggles to charge current and ramps up the CT pin. This starts a new switching cycle. The duty cycle of the oscillator determines the maximum PWM duty cycle. The switching frequency of the IC can be synchronized to an external frequency presented to the SYNCI pin. When pulses with amplitude over SYNCI input threshold are detected, the CT pin immediately ramps down the external capacitor and the VO pin is forced low. A new switching cycle begins when the CT pin reaches valley voltage. During synchronization, the oscillator charge current is reduced by 80 A, while discharge current is increased by 80 A. This effectively slows down the internal oscillator to avoid any race condition with the sync frequency. As a result, the sync frequency can be either higher or lower than the internal oscillator frequency. CS51220 is able to synchronize up to 500 kHz and down to 25% below CT frequency. The maximum duty cycle clamp is raised to 92% in synchronization mode. The original oscillator frequency is restored upon the removal of sync pulses.
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CS51220
The desired effect on the input ripple is illustrated in Figure 14. This is the input current for two power converters operating from a 36 V line.
Figure 12. Synchronization Input Timing
Figure 12 shows the sync input from one CS51220 into another. The delay between receiving the sync input and the start of the next switching cycle is 423 ns. This delay must be taken into account when establishing the total delay between two regulators. The SYNCO pin provides outgoing synchronization pulses whose delay can be programmed by setting the voltage on the VSD pin. The feature allows two converters to run at interleaved phases. This implementation significantly reduces the input ripple, and thus the number of input capacitors. The phase delay is achieved by turning on SYNCO output only after the CT pin voltage reaches the VSD voltage. Therefore, the phase delay varies linearly with the VSD voltage. The SYNCO output is reset during the falling edge of the CT pin. For minimum phase delay (~ 240 ns), tie the VSD pin to the ground. To entirely disable the SYNCO output, connect the VSD pin to VREF. The waveform in Figure 13 shows the CT ramp crossing the VSD voltage set at 1.41 V.
Figure 14. Input Current Ripple with Different Overlap Conditions
The top waveform in Figure 14 is the input current with the two supplies operating out of phase. The next down shows the same supplies but with both conduction times occurring simultaneously. The greatly increased ripple current can be observed. The last two waveforms are the two converters shown individually when operating out of phase. DESIGN GUIDELINES
Program Volt-Second Clamp
Feed forward voltage mode control provides the volt-second clamp which clamps the product of the line voltage and switch on time. For the circuit shown in Figure 15, the charging current of the CFF can be considered as a constant current equal to VIN/RFF , provided VIN is much greater than the FF pin voltage. Then the volt-second clamp provided by CS51220 is given by
VINTON(MAX) + 1.0RFFCFF
VIN
RFF
FF Pin CFF
Figure 13. Synchronization Output Timing
The delay from the point of crossing to the output of the sync signal is 240 ns. The time for the sync out voltage is measured at the +2.0 V level, which is the level that triggers the next CS51220.
Figure 15. An RC Network Provides Both Volt-Second Clamp and Feed Forward Control
Select the time constant of the FF pin RC network to provide desirable volt-second clamp.
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CS51220
Program Oscillator Frequency
CS51220 requires an external capacitor to program the oscillator frequency. The internally trimmed charge/discharge current determines the maximum duty cycle. The capacitor for a required switching frequency fS can be calculated by:
CT + 13400 * 95 fS
Synchronized Dual Converters with Soft Hiccup and Feed Forward
where: CT = Timing capacitance is in pF fS = Switching frequency is in kHz Figure 16 shows the relationship of CT and fS.
600 550 500 Frequency (kHz) 450 400 350 300 250 200 150 100
100 200 300 400 500 600
The circuits shown in Figures 17 and 18 illustrate typical applications for a dual output supply using independent but synchronized converters. These circuits demonstrate the use of the soft hiccup, feed forward, volt-second control and synchronization features of the CS51220. In Figure 17, the feed forward circuit has a volt-second constant of 82 V/s. This would limit the duty factor to 0.51 at 48 V input. With a turns ratio of 4:1 on the power transformer and 48 V input, a duty factor of 0.46 is required for 5.0 V output. This converter serves as the master synchronization generator. The voltage on the VSD pin establishes the delay as it is compared to the ramp generated on the CT pin. Adjustable synchronization allows the conduction time for the two converters to be adjusted so that they are not on at the same time. This greatly reduces the ripple current from the 48 V source. In Figure 18, the feed forward circuit has a volt-second constant of 63 V/s. This would limit the duty factor to 0.39 at 48 V input. With a turns ratio of 4:1 on the power transformer and 48 V input, a duty factor of 0.33 is required for 3.3V output.
CT (pF)
Figure 16. Operating Frequency
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TP1
D2
VIN
GND BST1
36-72 V C1 1.5 F 100 V R6 174 k Q1 MMFT1N10E 0.1 F C6 100 pF D5B MBRB2535CTL C5 470 pF D4 9.1 V MMSZ5239BT1 D3 15 V MMSZ5245BT1 R12 R10 36 10 k C2 D1 MMSD4148T1 R1 100 k R22 10 MMSD4148T1
R23 10
L2
VIN
1.0 H
C16 0.2 F 100 V
T1 L1
R11 100
C37 0.1 F 500 V
70:1 T2
6.8 H
C11 330 F D5A MBRB2535CTL
U1 VCC
TP2
R15 10
VOUT 5.0 V @ 5.0 A
FF
R4 150 k
R2 10 k
VREF CT VSD CS51220 ISET SS SYNCI SYNCO
C7 0.1 F C4 390 pF
ISENSE VO GND
20:5
C12 680 pF
C9 330 F
CS51220
NC GND
NCP4414
Figure 17. Additional Application Diagram, 5.0 V Output Converter Used As Sync Master for the Dual Converter
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UV OV COMP DISABLE ENABLE1 SYNC
R21 511 k
14 U4 VDD INA
C38 1000 pF
VORTN
C3 0.1 F
R3 7.5 k
VDD OUT OUT GND
R13 10 Q2 IRF634S R19 40.2 k
R5 64.9 k
TP3
R7 511 k
C10 100 pF 200 V
C36 R18 TP4 10 k
R16 182 U2 MOC213 R48 3.92 k R17 1.0 K
SYNC IN
C14 0.022 F C13
1.25 V
1000 pF
R8 15 k C35 1000 pF
R9 11.8 k
R20 13.3 k
100 pF
C18 1000 pF U3 TLV431ASNT1
R14 2.0 k
TP5
D6
BST1
36-72 V C32 1.5 F 100 V R37 10 MMSD4148T1 D7 R35 R36 36 10 k D8B MBRB2535CTL R24 137 k C22 0.1 F C23 100 pF MMSD4148T1
R38 10
VIN
GND
T3 L3
R34 100
C31 470 pF
70:1 T4
R39 10
6.8 H
C26 330 F D8A MBRB2535CTL
U5 FF VREF
TP6
VOUT 3.3 V @ 5.0 A
R25 10 k
R27 150 k
VCC ISENSE 20:5 VO GND SS SYNCI U4
C21 0.1 F
CT CS51220 VSD ISET UV
C20 390 pF
C25 680 pF
C27 330 F
VORTN
CS51220
SYNC OUT
R31 511 k
GND
NCP4414
Figure 18. Additional Application Diagram, 3.3 V Output Converter Synchronized to the 5.0 V Converter
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C39 1000 pF
15 OV SYNCO COMP DISABLE VDD INA NC ENABLE2 SYNC
R41 182 C33 1000 pF C24 1.0 F
C19 0.1 F
R26 5.11 k
R28 64.9 k
VDD OUT OUT GND
R40 10 Q3 MTB20N20E R44 40.2 k
TP7
R29 511 k
C28 100 pF 200 V
R43 2.21 k
R47 2.21 k U6 MOC213 R42 1.0 K
C29 0.022 F C30 100 pF
R45 24.3 k
R30 15 k
R32 11.8 k
R33 2.0 k
TP8
R49 3.3 k
U7 TLV431ASNT1 R48 220
CS51220
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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PUBLICATION ORDERING INFORMATION
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16
CS51220/D

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